For some applications, such as high-frequency interleaved data converters, misalignment and unintended overlap of the corresponding clock signals driving the individual converters can lead to undesired side effects. In general, clock signals with mismatched duty cycles can produce unintended (and undesired) behavior in corresponding circuits driven by such clock signals. However, there are a number of non-trivial issues associated with adjusting one or more duty cycles to eliminate such overlap or other unintended timing.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those in light of the present disclosure.